The video argues that advanced packaging has become a major bottleneck in AI chips, and that the bottleneck is especially acute because most of the capability still sits in Asia—above all at TSMC in Taiwan. Even chips made in the U.S. are often shipped back to Taiwan for packaging, though TSMC says it is building new U.S. packaging plants in Arizona. The piece also argues Intel and OSATs like Amkor and ASE may benefit as demand for CoWoS, EMIB, and other advanced packaging methods surges.
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This CNBC segment makes a clear thesis: in the AI boom, advanced packaging—not just leading-edge wafer fabrication—has become one of the most important constraints on how quickly the industry can ship usable chips. The report centers on TSMC’s role in packaging AI accelerators, especially NVIDIA’s, and shows how chips manufactured in the U.S. are still frequently shipped to Taiwan for packaging before they can enter the market. The reporting frames this as both a capacity problem and a geopolitical one, since the most critical packaging capacity remains concentrated in Asia. The explanation of why packaging matters is detailed and technical. The segment walks through how modern chips are assembled from multiple dies, HBM memory, substrates, interposers, bumps, and then increasingly 2.5D and 3D integration. …
Tactically, the market read is that AI-chip supply can stay tight if packaging remains constrained, so any name tied to CoWoS or advanced packaging capacity can react to supply-scarcity headlines. Near-term risk is that the bottleneck narrative persists until new Arizona and Intel capacity is visibly online.
Over the next several quarters, the base case is continued demand outpacing packaging supply, with gradual diversification into Intel, OSATs, and future U.S. TSMC capacity. The setup improves only if those capacity additions are clearly ramping faster than AI accelerator demand.
Structurally, the transcript argues that semiconductor power has become a full-stack manufacturing issue: advanced packaging is now part of the AI moat. Long run, concentrated packaging capacity in Asia remains a strategic vulnerability unless the U.S. rebuilds more of the assembly chain at home.
Nvidia has reserved most of TSMC's CoWoS advanced packaging capacity, leaving competitors concerned about access to the technology.
The transcript states that Nvidia has reserved the majority of TSMC's leading CoWoS packaging technology and that this has people worried because capacity is tight.
TSMC is expanding packaging capacity very rapidly, with CoWoS capacity growing at an 80% CAGR and SOIC capacity at 100% CAGR.
A speaker from TSMC says the company is increasing CoWoS and SOIC capacity at very high compound annual growth rates to respond to demand.
The US is likely to regain some lost semiconductor leadership through advanced packaging if TSMC's planned US facilities scale successfully.
The transcript concludes that bringing more advanced packaging to US soil may eventually help the US regain some of its long-lost lead in silicon.
Why are advanced packaging and CoWoS becoming such a bottleneck for AI chips?
The guest explains that AI demand for more GPUs and more HBM in a package has surged faster than companies planned for, so packaging capacity is tight. Advanced packaging is now as important as the die itself, and without enough capex it can become a major constraint.
What exactly is advanced packaging and how does it differ from standard packaging?
Advanced packaging combines multiple chips or chiplets from different technologies into one larger package with interconnects. The guest says it is the natural extension of Moore's law into the third dimension, beyond older standard packaging that mainly protected and contained a single chip.
Why did TSMC develop CoWoS and what problem does it solve for AI chips?
He says CoWoS puts HBM memory right beside the compute chip in a very efficient way, helping overcome the memory-wall problem. The latest CoWoS versions scale up the number of HBM stacks around the compute die for much higher performance.
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